An integrated circuit is formed on a semiconductor substrate and includes various devices, such as transistors, diodes, and/or resistors, configured and connected together to a functional circuit. Especially, the integrated circuit further includes field-effect transistors, such as metal-oxide-semiconductor FETs (MOSFETs) or complimentary MOSFETs, wherein each includes a gate electrode to control the channel region of the corresponding FET. When a semiconductor device such as a MOSFET is scaled down through various technology nodes, high k dielectric material and metal are adopted to form a gate stack. However, in a method to form metal gate stacks for n-type MOS (nMOS) transistors and p-type MOS (pMOS) transistors, various issues may arise when integrating the processes and materials for this purpose. For example, when a metal gate is formed through gate replacement, there is insufficient line-end process window since the gate dielectric layer is also formed on the sidewalls, leaving less opening to fill in with the metal or metal alloy. Furthermore, the profile of the metal gate stack is dependent on the layout of the gate-cut feature and the dielectric gate. This affects the threshold voltage and saturation current, and causes the variation of the device performance. Therefore, it is therefore desired to have a new device structure and the method making the same to address the above concerns with enhanced circuit performance.